% u.tex  93.06.10
% man circuit u .
% Copyright 1983-1992   Albert Davis
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\section{{\tt U}: Logic Device}
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\subsection{Syntax}
\begin{verse}
{\tt U}{\it xxxxxxx} {\tt vdd} {\it out in1 in2 ... family gatetype}
\end{verse}
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\subsection{Purpose}

Logic element for mixed or logic mode simulation.
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\subsection{Comments}

A sample 2 input nand gate might be: {\tt U102 34 5 2 3 cmos nand}.  The
input pins are connected to nodes 2 and 3.  The output is at node 5.  Node
34 is the power supply.

The logic element behaves differently depending on the options {\tt analog},
{\tt mixed}, or {\tt digital}.  You set one of these with the {\tt options}
command.  {\tt Analog} mode substitutes a subcircuit for the gate for full
analog simulation.  {\tt Digital} mode simulates the gate as a digital
device as in an event driven gate level logic simulator.  {\tt Mixed} mode
applies heuristics to decide whether to use analog or digital for each gate.

In {\tt analog} mode the logic ({\tt U}) device is almost the same as a
subcircuit ({\tt X}).  The subcircuit is user defined for each gate type
used.  A {\tt .subckt} defines the analog equivalent of a logic element.
The name of the subcircuit is made by concatenating the {\em family}, {\em
gatetype}, and the number of inputs.  For example, if the {\em family} is
{\tt cmos} and the {\em gatetype} is {\tt nand} and it has two inputs, the
name of the subcircuit is {\tt cmosnand2}.  So, the gate in the first
paragraph becomes equivalent to: {\tt X 34 5 2 3 cmosnand2}.  You then need
to define the subcircuit using the standard {\tt .subckt} notation.  You can
probe the internal elements the same as an ordinary subcircuit.

The {\tt digital} mode uses simple boolean expressions to compute the
output, just like a gate level logic simulator.  In this case the output is
computed by L(5) = not(L(2) and L(3)) where L(2) is the logic state at node
2.  The simulator exploits latency so it will only compute the output if one
of the inputs changes.  The output actually changes after a delay, specified
in the {\tt .model} statement.  There are no conversions between digital and
analog where gates connect together.  There will be an automatic conversion
from analog to digital for any input that is driven by an analog device.
There will be an automatic conversion from digital to analog for any output
that drives an analog device.  These conversions will only be done if they
are needed.  You can probe the analog value at any node.  The probe will
automatically request the conversion if it needs it.  There is no internal
subcircuit so it is an error to probe the internal elements.

The {\tt mixed} mode is a combination of analog and digital modes on a gate
by gate basis.  Some gates will be analog.  Some will be digital.  This will
change as the simulation runs based on the quality of the signals.  You need
to specify a {\tt .subckt} as you do for the analog mode, but the simulator
may not use it.  You can usually not probe the elements inside the
sibcircuit because they come and go.
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\subsection{Element Parameters}

{\em Family} refers to the logic family {\tt .model} statement.

{\em Gatetype} is the type of logic gate:

\begin{description}

\item[{\tt AND}]

\item[{\tt NAND}]

\item[{\tt OR}]

\item[{\tt NOR}]

\item[{\tt XOR}]

\item[{\tt INV}]

\end{description}

More will be added including counters, flip-flops and memory cells.
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\subsection{Model Parameters}

\subsubsection{Parameters used in digital mode}
\begin{description}

\item[{\tt DElay} = {\it x}] Propagation delay.  (Seconds) (Default = 1e-9)
The propagation delay of a simple gate when simulated in logic mode.

\end{description}
%----------------------------------------
\subsubsection{Parameters used in conversion both ways}
\begin{description}

\item[{\tt VMAx} = {\it x}] Nominal logic 1.  (Volts) (Default = 5.) The
nominal value for a logic 1.

\item[{\tt VMIn} = {\it x}] Nominal logic 0.  (Volts) (Default = 0.) The
nominal value for a logic 0.

\end{description}
%----------------------------------------
\subsubsection{Digital to Analog conversion}
\begin{description}

\item[{\tt RIse} = {\it x}] Rise time. (Seconds) (Default = delay / 2) The
nominal rise time of a logic signal.  This will be the rise time when a
logic signal is converted to analog.

\item[{\tt FAll} = {\it x}] Fall time. (Seconds) (Default = delay / 2) The
nominal fall time of a logic signal.  This will be the fall time when a
logic signal is converted to analog.

\item[{\tt RS} = {\it x}] Series resistance, strong. (Ohms) (Default =
100.)  The resistance in series with the output when a logic gate drives
analog circuitry.

\item[{\tt RW} = {\it x}] Series resistance, weak. (Ohms) (Default = 1e9)
The output resistance in a high impedance state.

\end{description}
%----------------------------------------
\subsubsection{Analog to Digital conversion}
\begin{description}

\item[{\tt THH} = {\it x}] Threshold high.  (Unitless) (Default = .75) The
threshold for the input to cross from transition to high expressed as a
fraction of the difference between high and low values.  (Low = 0.  High =
1.)

\item[{\tt THL} = {\it x}] Threshold low.  (Unitless) (Default = .25) The
threshold for the input to cross from transition to low expressed as a
fraction of the difference between high and low values.  (Low = 0.  High =
1.)

\end{description}
%----------------------------------------
\subsubsection{Mode decision parameters}
\begin{description}

\item[{\tt MR} = {\it x}] Margin rising.  (Unitless) (Default = 5) How much
worse than nominal the analog input rise time can be and still be accepted
as clean enough for logic simulation.

\item[{\tt MF} = {\it x}] Margin falling.  (Unitless) (Default = 5) How much
worse than nominal the analog input fall time can be and still be accepted
as clean enough for logic simulation.

\item[{\tt OVer} = {\it x}] Overshoot limit.  (Unitless) (Default = .1) How
much overshoot can a signal have and still be accepted as clean enough for
logic simulation, expressed as a fraction of the difference between high and
low values.  (Low = 0.  High = 1.)

\end{description}
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\subsection{Probes}

\begin{description}

\item[{\tt V}] Output voltage.

\end{description}

In this release, there are no probes available in AC analysis except for the
internal elements.  Internal elements in the analog model are available, but
they come and go so they may be unreliable.  More parameters will be added.

You can probe the logic value at any node.  See the {\tt print} command for
details.
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