| |
|
[General Information]
|
| Processor Name: | Intel Celeron 300A
|
| Original Processor Frequency: | 300.0 MHz
|
| Original Processor Frequency [MHz]: | 300
|
| |
|
| CPU ID: | 00000660
|
| CPU Vendor: | GenuineIntel
|
| CPU Stepping: | A0
|
| CPU Code Name: | Mendocino
|
| CPU Technology: | 250 nm
|
| CPU QDF: | Q618
|
| CPU S-Spec: | SL2WM (SEPP Rev1)
|
| CPU Thermal Design Power (TDP): | 19.05 W
|
| CPU Max. Case Temperature (Tcase_max): | 85 �C
|
| CPU Platform: | Slot1 (SECC)
|
| Microcode Update Revision: | 4
|
| |
|
| Number of CPU Cores: | 1
|
| Number of Logical CPUs: | 1
|
| |
|
[Operating Points]
|
| CPU HFM (Base): | 300.0 MHz = 4.50 x 66.7 MHz
|
| CPU Current: | 298.5 MHz = 4.50 x 66.3 MHz
|
| |
|
| CPU Bus Type: | FSB
|
| |
|
[Cache and TLB]
|
| L1 Cache: | Instruction: 16 KBytes, Data: 16 KBytes
|
| L2 Cache: | Integrated: 128 KBytes
|
| Instruction TLB: | 4 KB Pages, 4-way set associative, 32 entries
|
| Data TLB: | 4 KB Pages, 4-way set associative, 64 entries
|
| |
|
[Standard Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| Pentium-style Model Specific Registers | Present
|
| Physical Address Extension | Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip / PGE (AMD) | Not Present
|
| Fast System Call | Present
|
| Memory Type Range Registers | Present
|
| Page Global Feature | Present
|
| Machine Check Architecture | Present
|
| CMOV Instruction | Present
|
| Page Attribute Table | Present
|
| 36-bit Page Size Extensions | Present
|
| Processor Number | Not Present
|
| CLFLUSH Instruction | Not Present
|
| Debug Trace and EMON Store | Not Present
|
| Internal ACPI Support | Not Present
|
| MMX Technology | Present
|
| Fast FP Save/Restore (IA MMX-2) | Present
|
| Streaming SIMD Extensions | Not Present
|
| Streaming SIMD Extensions 2 | Not Present
|
| Self-Snoop | Not Present
|
| Multi-Threading Capable | Not Present
|
| Automatic Clock Control | Not Present
|
| IA-64 Processor | Not Present
|
| Signal Break on FERR | Not Present
|
| Virtual Machine Extensions (VMX) | Not Present
|
| Safer Mode Extensions (Intel TXT) | Not Present
|
| Streaming SIMD Extensions 3 | Not Present
|
| Supplemental Streaming SIMD Extensions 3 | Not Present
|
| Streaming SIMD Extensions 4.1 | Not Present
|
| Streaming SIMD Extensions 4.2 | Not Present
|
| AVX Support | Not Present
|
| Fused Multiply Add (FMA) | Not Present
|
| Carryless Multiplication (PCLMULQDQ)/GFMUL | Not Present
|
| CMPXCHG16B Support | Not Present
|
| MOVBE Instruction | Not Present
|
| POPCNT Instruction | Not Present
|
| XSAVE/XRSTOR/XSETBV/XGETBV Instructions | Not Present
|
| XGETBV/XSETBV OS Enabled | Not Present
|
| Float16 Instructions | Not Present
|
| AES Cryptography Support | Not Present
|
| Random Number Read Instruction (RDRAND) | Not Present
|
| Extended xAPIC | Not Present
|
| MONITOR/MWAIT Support | Not Present
|
| Thermal Monitor 2 | Not Present
|
| Enhanced SpeedStep Technology | Not Present
|
| L1 Context ID | Not Present
|
| Send Task Priority Messages Disabling | Not Present
|
| Processor Context ID | Not Present
|
| Direct Cache Access | Not Present
|
| TSC-deadline Timer | Not Present
|
| Performance/Debug Capability MSR | Not Present
|
| IA32 Debug Interface Support | Not Present
|
| 64-Bit Debug Store | Not Present
|
| CPL Qualified Debug Store | Not Present
|
| |
|
[Enhanced Features]
|
| Thermal Monitor 1: | Not Supported
|
| Thermal Monitor 2: | Not Supported
|
| Enhanced Intel SpeedStep (GV3): | Not Supported
|
| Bi-directional PROCHOT#: | N/A
|
| Extended Auto-HALT State C1E: | Not Supported
|
| MLC Streamer Prefetcher | Not Supported
|
| MLC Spatial Prefetcher | Not Supported
|
| DCU Streamer Prefetcher | Not Supported
|
| DCU IP Prefetcher | Not Supported
|
| Intel Dynamic Acceleration (IDA) Technology: | Not Supported
|
| Intel Dynamic FSB Switching: | Not Supported
|
| Intel Turbo Boost Technology: | Not Supported
|
| Programmable Ratio Limits: | Not Supported
|
| Programmable TDC/TDP Limits: | Not Supported
|
| Hardware Duty Cycling: | Not Supported
|
| Intel Speed Select: | Not Supported
|
| |
|
[Memory Ranges]
|
| Maximum Physical Address Size: | 36-bit (64 (null))
|
| Maximum Virtual Address Size: | 32-bit (4 (null))
|
[MTRRs]
|
| |
|
[General Module Information]
|
| Module Number: | 0
|
| Module Size: | 64 MBytes
|
| Memory Type: | SDRAM
|
| Error Check/Correction: | None
|
| Memory Speed: | 100.0 MHz (PC100)
|
| Module Manufacturer: | Infineon
|
| Module Part Number: | HYS64V8200GU-8
|
| Module Serial Number: | 1562312896
|
| Module Manufacturing Date: | Year: 2052, Week: 70
|
| |
|
[Module Characteristics]
|
| Module Width: | 64-bits
|
| Module Voltage: | LVTTL
|
| SPD Revision: | 1.2
|
| Number Of Rows: | 1
|
| Row Address Bits: | 12
|
| Column Address Bits: | 9
|
| Number Of Banks: | 4
|
| |
|
[Module timing]
|
| Supported Burst Lengths: | 1, 2, 4, 8
|
| Refresh Rate: | Normal (15.625 us)
|
| Min. Back-to-Back Clock Delay: | 1
|
| Supported CAS Latencies (tCAS): | 3.0, 2.0
|
| Min. RAS-to-CAS Delay (tRCD): | 20.00 ns
|
| Min. Row Precharge Time (tRP): | 20.00 ns
|
| Min. RAS Pulse Width (tRAS): | 45 ns
|
| |
|
| Supported Module Timing at 100.0 MHz: | 3.0-2-2-5
|
| Supported Module Timing at 100.0 MHz: | 2.0-2-2-5
|
| Supported Module Timing at 66.7 MHz: | 2.0-2-2-3
|
| |
|
| Min. Row-Activate To Row-Activate Delay (tRRD): | 16.00 ns
|
| Supported CS Latency: | 0
|
| Supported WE Latency: | 0
|
| |
|
[Features]
|
| Early RAS# Precharge: | Not Supported
|
| Auto Precharge: | Supported
|
| Precharge All: | Supported
|
| Write1/ReadBurst: | Not Supported
|
| Buffered Address/Control Inputs: | Not Supported
|
| Registered Address/Control Inputs: | Not Supported
|
| On-card PLL For Clock: | Not Supported
|
| Buffered DQMB Inputs: | Not Supported
|
| Registered DQMB Inputs: | Not Supported
|
| Differential Clock Input: | Not Supported
|
| Redundant Row Address: | Not Supported
|
| |
|
[Intel-defined characteristics]
|
| Intel-defined Concurrent AutoPrecharge: | Supported
|
| CAS Latency 2: | Supported
|
| CAS Latency 3: | Supported
|
| Max. Junction Temperature: | 100 C
|
| |
|
[General Information]
|
| Device Name: | Intel 82443BX/ZX Host Bridge/Controller [B-1]
|
| Original Device Name: | Intel 82443BX/ZX Host Bridge/Controller [B-1]
|
| Device Class: | Host-to-PCI Bridge
|
| Revision ID: | 2 [B-1]
|
| PCI Address (Bus:Device:Function) Number: | 0:0:0
|
| PCI Latency Timer: | 64
|
| Hardware ID: | PCI\VEN_8086&DEV_7190&SUBSYS_00000000&REV_02
|
| |
|
[System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| Memory Base Address 0 | 44000000
|
| |
|
[Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| |
|
[440BX Configuration]
|
| Host Bus Fast Data Ready: | Disabled
|
| ECC - EDO Static Drive Mode: | Disabled
|
| IDSEL redirection: | Allocate IDSEL1/AD12 to bridge
|
| WSC# handshake: | Disabled
|
| Host/DRAM Frequency: | 66 MHz
|
| AGP-to-PCI Access: | Enabled
|
| PCI Agent to Apreture Access: | Enabled
|
| Aperture Access Global: | Enabled
|
| DRAM Data Integrity Mode: | Non-ECC
|
| ECC Diagnostics Mode: | Disabled
|
| MDA: | Absent
|
| USWC Write Posting: | Enabled
|
| In-Order Queue Depth: | Maximum (4)
|
| |
|
[DRAM Control]
|
| Module Mode Configuration: | Self-refresh entry staggered
|
| DRAM type: | SDRAM
|
| DRAM Refresh Rate: | 15.6 us
|
| |
|
[DRAM Timing]
|
| EDO RASx# Wait State: | 2 tASR
|
| EDO CASx# Wait State: | 2 Tasc
|
| |
|
[Programmable Attribute Map]
|
| Segment F000-FFFF: | Read-only
|
| Segment C000-C3FF: | Read-only
|
| Segment C400-C7FF: | Read-only
|
| Segment C800-CBFF: | No access
|
| Segment CC00-CFFF: | No access
|
| Segment D000-D3FF: | No access
|
| Segment D400-D7FF: | No access
|
| Segment D800-DBFF: | No access
|
| Segment DC00-DFFF: | No access
|
| Segment E000-E3FF: | Read-only
|
| Segment E400-E7FF: | Read-only
|
| Segment E800-EBFF: | Read-only
|
| Segment EC00-EFFF: | Read/Write
|
| |
|
[Fixed DRAM Hole Control]
|
| Hole Enable: | None
|
| |
|
[Memory Buffer Strength Control]
|
| MECC[7:0] (2): | 1x
|
| MECC[7:0] (1): | 1x
|
| CSB7#/CKE5: | 1x
|
| CSA7#/CKE3: | 1x
|
| CSB6#/CKE4: | 1x
|
| CSA6#/CKE2: | 1x
|
| CSA5#/RASA5#, CSB5#/RASB5#: | 1x
|
| CSA4#/RASA4#, CSB4#/RASB4#: | 1x
|
| CSA3#/RASA3#, CSB3#/RASB3#: | 1x
|
| CSA2#/RASA2#, CSB2#/RASB2#: | 1x
|
| CSA1#/RASA1#, CSB1#/RASB1#: | 1x
|
| CSA0#/RASA0#, CSB0#/RASB5#: | 1x
|
| DQMA5/CASA5#: | 1x
|
| DQMA1/CASA1#: | 1x
|
| DQMB5/CASB5#: | 1x
|
| DQMB1/CASB1#: | 1x
|
| DQMA[7:6,4:2,0], CASA[7:6,4:2,0]#: | 1x
|
| CKE1/GCKE: | 1x
|
| CKE0/FENA: | 3x
|
| |
|
[Memory Buffer Strength Control]
|
| MAA[13:0], WEA#, SRASA#, SCASA#: | 1x
|
| MAB..., WEB#, SRASB#, SCASB#: | 1x
|
| MD[63:0] (2): | 1x
|
| MD[63:0] (1): | 1x
|
| |
|
[System Management RAM control]
|
| SMM Space Open: | No
|
| SMM Space Closed: | No
|
| SMM Space Locked: | No
|
| SMRAM Enable: | Enabled
|
| SMM Space Base Segment: | A000-BFFF
|
| |
|
[Extended SMRAM Control]
|
| High SMRAM: | Disabled
|
| SMRAM Caching: | Enabled
|
| L1 Caching of SMRAM: | Enabled
|
| L2 Caching of SMRAM: | Enabled
|
| TSEG size: | 128K
|
| TSEG: | Disabled
|
| |
|
[SDRAM Row Page Size]
|
| ROW7 page size: | 2 KB
|
| ROW6 page size: | 2 KB
|
| ROW5 page size: | 2 KB
|
| ROW4 page size: | 2 KB
|
| ROW3 page size: | 2 KB
|
| ROW2 page size: | 2 KB
|
| ROW1 page size: | 4 KB
|
| ROW0 page size: | 4 KB
|
| |
|
[SDRAM Control Register]
|
| Idle/pipeline DRAM leadoff delay: | Add 1 Clock
|
| SDRAM Mode Select: | Normal Operation
|
| SDRAMPWR: | Disabled
|
| Leadoff Command Timing: | 3 CS# clocks
|
| CAS# Latency: | 2 DCLKs
|
| SDRAM RAS#-to-CAS# Delay: | 2 clocks
|
| SDRAM RAS# Precharge: | 2 clocks
|
| |
|
[Paging Policy Register]
|
| Banks per ROW0: | 2 banks
|
| Banks per ROW1: | 2 banks
|
| Banks per ROW2: | 2 banks
|
| Banks per ROW3: | 2 banks
|
| Banks per ROW4: | 2 banks
|
| Banks per ROW5: | 2 banks
|
| Banks per ROW6: | 4 banks
|
| Banks per ROW7: | 4 banks
|
| DRAM Idle Timer: | 8 clocks
|
| |
|
[Power Management Control]
|
| SDRAM Power-Down: | Disabled
|
| ACPI Control Register: | Disabled
|
| Suspend Refresh Type: | CBR Mode
|
| Normal Refresh: | Enabled
|
| Quick-start Mode: | Disabled
|
| Gated Clock Enable: | Enabled
|
| AGP Status: | Enabled
|
| CPU Reset w/o PCIRST: | Disabled
|
| |
|
[Suspend CBR Refresh Rate]
|
| Suspend CBR Refresh Rate Auto Adjust: | Disabled
|
| Suspend CBR Refresh Rate: | 56 OSCCLKs
|
| |
|
[Error Command Register]
|
| SERR# on AGP Non-snoopable Access: | Disabled
|
| SERR# on Invalid AGP DRAM Access: | Disabled
|
| SERR# on Access to Invalid GATTE: | Disabled
|
| SERR# on Receiving Target Abort: | Disabled
|
| SERR# on Thermal DRAM Throttling: | Disabled
|
| SERR# Mode: | Asserted for 1 PCICLK
|
| SERR# on Multi-bit Parity/ECC Error: | Disabled
|
| SERR# on Single-bit ECC Error: | Disabled
|
| |
|
[Error Status Register]
|
| Read Thermal Throttling: | Not occurred
|
| Write Thermal Throttling: | Not occurred
|
| AGP Non-snoopable Access Outside GATTE: | Not occurred
|
| Invalid AGP Non-snoopable DRAM Read Access: | Not occurred
|
| Invalid GATTE: | Not occurred
|
| First Multi-bit Error: | Row: 0
|
| Multi-bit Error: | Not occurred
|
| First Single-bit Error: | Row: 0
|
| Single-bit Error: | Not occurred
|
| |
|
[AGP Status Register]
|
| Max. AGP Request Queue Depth: | 31
|
| AGP Side Band Addressing: | Supported
|
| Supported AGP Data Transfer: | 1x and 2x
|
| |
|
[AGP Command Register]
|
| AGP Sideband Addressing: | Enabled
|
| AGP Status: | Enabled
|
| Current AGP Transfer Rate: | 2x
|
| |
|
[AGP Control Register]
|
| Snoopable Writes In Order with AGP Read: | Enabled
|
| GA Write-AGP Read Sync.: | Disabled
|
| GA TLB: | Enabled
|
| |
|
[Aperture Size Control]
|
| Graphics Aperture size: | 64M
|
| |
|
[Aperture Translation Table]
|
| Aperture Translation Table Base: | 3FEE000
|
| |
|
[Memory Buffer Frequency Select]
|
| MAA[13:0], WEA#, SRASA#, SCASA#: | 66 MHz
|
| MAB..., WEB#, SRASB#, SCASB#: | 66 MHz
|
| MD[63:0] (control 2): | 66 MHz
|
| MD[63:0] (control 1): | 66 MHz
|
| MECC[7:0] (control 2): | 66 MHz
|
| MECC[7:0] (control 1): | 66 MHz
|
| CSB7#/CKE5: | 66 MHz
|
| CSA7#/CKE3: | 66 MHz
|
| CSB6#/CKE4: | 66 MHz
|
| CSA6#/CKE2: | 66 MHz
|
| CSA5#/RASA5#, CSB5#/RASB5#: | 66 MHz
|
| CSA4#/RASA4#, CSB4#/RASB4#: | 66 MHz
|
| CSA3#/RASA3#, CSB3#/RASB3#: | 66 MHz
|
| CSA2#/RASA2#, CSB2#/RASB2#: | 66 MHz
|
| CAS1#/RASA1#, CSB1#/RASB1#: | 66 MHz
|
| CSA0#/RASA0#, CSB0#/RASB0#: | 66 MHz
|
| DQMA5/CASA5#: | 66 MHz
|
| DQMA1/CASA1#: | 66 MHz
|
| DQMB5/CASB5#: | 66 MHz
|
| DQMB1/CASB1#: | 66 MHz
|
| DQMA[7:6,4:2,0], CASA[7:6,4:2,0]#: | 66 MHz
|
| CKE1/GCKE: | 66 MHz
|
| CKE0/FENA: | 66 MHz
|
| |
|
[Buffer Control Register]
|
| Strong Pull-Up: | Disabled
|
| Weak Pull-Up: | Enabled
|
| Strong Pull-Down: | Disabled
|
| Weak Pull-Down: | Enabled
|
| |
|
[General Information]
|
| Device Name: | Intel 82371EB PCI ISA IDE Xcelerator 4 - PIIX4E [A-0]
|
| Original Device Name: | Intel 82371EB PCI ISA IDE Xcelerator 4 - PIIX4E [A-0]
|
| Device Class: | PCI-to-ISA Bridge
|
| Revision ID: | 2
|
| PCI Address (Bus:Device:Function) Number: | 0:20:0
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_8086&DEV_7110&SUBSYS_00000000&REV_02
|
| |
|
[System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| |
|
[Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Capable
|
| |
|
[ISA I/O Recovery Timer]
|
| 16-bit I/O Recovery Time: | 3 SYSCLKs
|
| 16-bit I/O Recovery: | Disabled
|
| 8-bit I/O Recovery Time: | 8 SYSCLKs
|
| 8-bit I/O Recovery: | Disabled
|
| DMA Res. Page Reg. Aliasing: | Disabled
|
| |
|
[X-Bus Chip Select]
|
| Micro Controller Location: | Disabled
|
| 1-Meg Extended BIOS: | Disabled
|
| I/O APIC: | Disabled
|
| Extended BIOS: | Disabled
|
| Lower BIOS (E0000h): | Disabled
|
| Coprocessor Error: | Enabled (FERR# -> IRQ13)
|
| IRQ12/Mouse Function: | Standard IRQ12
|
| BIOSCS# Write Protect: | Disabled (Read only)
|
| KBCCS# Keyboard Controller: | Disabled
|
| RTCCS#/RTCALE RTC: | Disabled
|
| |
|
[PIRQA Route Control]
|
| IRQ Routing: | Disabled
|
| IRQ Number: | 0
|
| |
|
[PIRQB Route Control]
|
| IRQ Routing: | Disabled
|
| IRQ Number: | 0
|
| |
|
[PIRQC Route Control]
|
| IRQ Routing: | Enabled
|
| IRQ Number: | 11
|
| |
|
[PIRQD Route Control]
|
| IRQ Routing: | Enabled
|
| IRQ Number: | 11
|
| |
|
[Serial IRQ Control]
|
| Serial IRQ: | Disabled
|
| Serial IRQ Mode: | Quiet mode
|
| Serial IRQ Frame Size: | 17
|
| Start Frame Pulse Width: | 4 Clocks
|
| |
|
[Top Of Memory]
|
| Top of ISA Memory: | 16 MBytes
|
| ISA/DMA Lower BIOS Forward: | Disabled
|
| A000/B000 Segment Forward: | Disabled
|
| ISA/DMA 512K-640K Region Forward: | Enabled
|
| |
|
[Miscellaneous Status]
|
| SERR# on Delayed Transaction: | Disabled
|
| Host-to-PCI Bridge Retry: | Enabled
|
| |
|
[Motherboard DMA Control]
|
| Type F and DMA Buffer: | Disabled
|
| DMA Channel: | 4
|
| |
|
[Motherboard DMA Control]
|
| Type F and DMA Buffer: | Disabled
|
| DMA Channel: | 4
|
| |
|
[APIC Base Address Relocation]
|
| A12 Mask: | Disabled
|
| APIC Base Address: | FEC00000
|
| |
|
[Deterministic Latency Control]
|
| SERR# on Delayed Transaction Timeout: | Disabled
|
| USB Passive Release: | Enabled
|
| Passive Release: | Enabled
|
| Delayed Transactions: | Enabled
|
| |
|
[PCI DMA Configuration]
|
| DMA CH7 Select: | Normal ISA
|
| DMA CH6 Select: | Normal ISA
|
| DMA CH5 Select: | Normal ISA
|
| DMA CH3 Select: | Normal ISA
|
| DMA CH2 Select: | Normal ISA
|
| DMA CH1 Select: | Normal ISA
|
| DMA CH0 Select: | Normal ISA
|
| |
|
[Distributed DMA (CH0-3) slave base pointer]
|
| Slave Channel I/O Address: | 0
|
| |
|
[Distributed DMA (CH5-7) slave base pointer]
|
| Slave Channel I/O Address: | 0
|
| |
|
[General Configuration]
|
| KBCCS#/GPO26 Pin Select: | KBCCS#
|
| RTCALE/GPO25 Pin Select: | RTCALE
|
| RTCCS#/GPO24 Pin Select: | RTCCS#
|
| XOE# and XDIR#/GPO[22:23] Pin Select: | XOE# and XDIR#
|
| RI#/GPI12 Pin Select: | RI#
|
| LID/GPI10 Pin Select: | LID
|
| BATLOW#/GPI9 Pin Select: | BATLOW#
|
| THRM#/GPI8 Pin Select: | GPI8
|
| SUS_STAT2#/GPO21 Pin Select: | SUS_STAT2#
|
| SUS_STAT1#/GPO20 Pin Select: | SUS_STAT1#
|
| ZZ/GPO19 Pin Select: | ZZ
|
| PCI_STP#/GPO18 Pin Select: | PCI_STP#
|
| CPU_STP#/GPO17 Pin Select: | CPU_STP#
|
| SUSB# and SUSC#/GPO[15:16] Pin Select: | SUSB# and SUSC#
|
| SERIRQ/GPI7 Pin Select: | GPI7
|
| SMBALERT#/GPI11 Pin Select: | SMBALERT#
|
| IRQ8#/GPI6 Pin Select: | IRQ8#
|
| Secondary IDE Signal Tri-state: | Disabled
|
| Primary IDE Signal Tri-state: | Disabled
|
| PC/PCI REQC, GNTC/GPI[4,11] Pin Select: | GPI[4,11]
|
| PC/PCI REQB, GNTB/GPI[3,10] Pin Select: | GPI[3,10]
|
| PC/PCI REQA, GNTA/GPI[2,9] Pin Select: | GPI[2,9]
|
| PnP Address Decode: | Enabled
|
| Alternate Access Mode: | Disabled
|
| IDE Signal Split: | Disabled
|
| Positive/Subtractive Decode: | Subtractive
|
| ISA/EIO Select: | ISA
|
| |
|
[Real-time Clock Configuration]
|
| RTC Positive Decode: | Disabled
|
| Lock Upper RTC RAM Bytes: | Absent
|
| Lock Lower RTC RAM Bytes: | Absent
|
| Upper RTC RAM: | Disabled
|
| RTC: | Disabled
|
| |
|
[General Information]
|
| Device Name: | Intel 82371AB/EB PIIX4/E - IDE Controller [B-0/A-0]
|
| Original Device Name: | Intel 82371AB/EB PIIX4/E - IDE Controller [B-0/A-0]
|
| Device Class: | IDE Controller
|
| Revision ID: | 1
|
| PCI Address (Bus:Device:Function) Number: | 0:20:1
|
| PCI Latency Timer: | 64
|
| Hardware ID: | PCI\VEN_8086&DEV_7111&SUBSYS_00000000&REV_01
|
| |
|
[System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| I/O Base Address 4 | 2040
|
| |
|
[Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Capable
|
| |
|
[IDE Timing Modes (Primary Channel)]
|
| IDE Decode: | Enabled
|
| Slave IDE Timing Register: | Disabled
|
| IORDY# Sample Point: | 3 clocks
|
| Recovery Time: | 2 clocks
|
| DMA Timing Only (drive 1): | Disabled
|
| Prefetch And Posting (drive 1): | Disabled
|
| IORDY# Sample Point (drive 1): | Disabled
|
| Fast Timing Bank (drive 1): | Disabled
|
| DMA Timing Only (drive 0): | Disabled
|
| Prefetch And Posting (drive 0): | Enabled
|
| IORDY# Sample Point (drive 0): | Enabled
|
| Fast Timing Bank (drive 0): | Enabled
|
| |
|
[IDE Timing Modes (Secondary Channel)]
|
| IDE Decode: | Enabled
|
| Slave IDE Timing Register: | Disabled
|
| IORDY# Sample Point: | 5 clocks
|
| Recovery Time: | 4 clocks
|
| DMA Timing Only (drive 1): | Disabled
|
| Prefetch And Posting (drive 1): | Disabled
|
| IORDY# Sample Point (drive 1): | Disabled
|
| Fast Timing Bank (drive 1): | Disabled
|
| DMA Timing Only (drive 0): | Disabled
|
| Prefetch And Posting (drive 0): | Disabled
|
| IORDY# Sample Point (drive 0): | Disabled
|
| Fast Timing Bank (drive 0): | Disabled
|
| |
|
[Slave IDE Timing]
|
| Secondary Drive 1 IORDY# Sample Point: | 5 clocks
|
| Secondary Drive 1 Recovery Time: | 4 clocks
|
| Primary Drive 1 IORDY# Sample Point: | 5 clocks
|
| Primary Drive 1 Recovery Time: | 4 clocks
|
| |
|
[Ultra DMA/33 Control]
|
| Primary Drive 0 UDMA: | Enabled
|
| Primary Drive 1 UDMA: | Disabled
|
| Secondary Drive 0 UDMA: | Disabled
|
| Secondary Drive 1 UDMA: | Disabled
|
| |
|
[Ultra DMA/33 Timing]
|
| Primary Drive 0 Cycle Time: | CT=2 PCICLK, RP=4 PCICLK
|
| Primary Drive 1 Cycle Time: | CT=4 PCICLK, RP=6 PCICLK
|
| Secondary Drive 0 Cycle Time: | CT=4 PCICLK, RP=6 PCICLK
|
| Secondary Drive 1 Cycle Time: | CT=4 PCICLK, RP=6 PCICLK
|
| |
|
[General Information]
|
| Device Name: | Intel 82371AB/EB PIIX4/E - USB Host Controller [B-0/A-0]
|
| Original Device Name: | Intel 82371AB/EB PIIX4/E - USB Host Controller [B-0/A-0]
|
| Device Class: | USB UHCI Controller
|
| Revision ID: | 1
|
| PCI Address (Bus:Device:Function) Number: | 0:20:2
|
| PCI Latency Timer: | 64
|
| Hardware ID: | PCI\VEN_8086&DEV_7112&SUBSYS_00000000&REV_01
|
| |
|
[System Resources]
|
| Interrupt Line: | IRQ11
|
| Interrupt Pin: | INTD#
|
| I/O Base Address 4 | 2020
|
| |
|
[Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Capable
|
| |
|
| USB Version Supported: | 1.0
|
| |
|
[Serial Bus Release Number:]
|
| USB Specification Release Number: | 1.0
|
| |
|
[Legacy Support]
|
| USB PIRQ: | Enabled
|
| Trap Caused By Write To PORT 64h: | No
|
| Trap Caused By Read From PORT 64h: | No
|
| Trap Caused By Write To PORT 60h: | No
|
| Trap Caused By Read From PORT 60h: | No
|
| SMI At End Of A20GATE Pass-Through: | Disabled
|
| A20GATE Pass-Through Sequence In Progress: | No
|
| A20GATE Pass-Through Sequence: | Disabled
|
| Trap/SMI On USB IRQ: | Disabled
|
| Trap/SMI On PORT 64h Write: | Disabled
|
| Trap/SMI On PORT 64h Read: | Disabled
|
| Trap/SMI On PORT 60h Write: | Disabled
|
| Trap/SMI On PORT 60h Read: | Disabled
|
| |
|
[Miscellaneous Status]
|
| RTC Index Read: | Disabled
|
| |
|
[General Information]
|
| Device Name: | Intel 82371EB PIIX4E - Power Management Controller [A-0]
|
| Original Device Name: | Intel 82371EB PIIX4E - Power Management Controller [A-0]
|
| Device Class: | Other Bridge
|
| Revision ID: | 2
|
| PCI Address (Bus:Device:Function) Number: | 0:20:3
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_8086&DEV_7113&SUBSYS_00000000&REV_02
|
| |
|
[System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| |
|
[Features]
|
| Bus Mastering: | Disabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Capable
|
| |
|
[Power-management I/O Ports]
|
| PM I/O Base Address: | F800
|
| |
|
[COUNT A]
|
| Slow Burst Count: | 0
|
| Idle Timer Count: | 0
|
| Device 11 Idle Timer Resolution: | 1 second
|
| Idle Timer Count C: | 0
|
| Idle Timer Count B: | 0
|
| SW Idle Timer Count: | 0
|
| Device 3 Idle Timer Resolution: | 8 second
|
| Device 2 Idle Timer Resolution: | 8 second
|
| Device 1 Idle Timer Resolution: | 8 second
|
| Device 0 Idle Timer Resolution: | 8 second
|
| Idle Timer Count A: | 0
|
| |
|
[COUNT B]
|
| Video Status: | Inactive
|
| Bus Master Timer Count: | 0
|
| Device 8 Idle Timer Resolution: | 1 second
|
| ZZ Signal: | Disabled
|
| Thermal Duty Cycle: |
|
| Processor PLL Lock Cnt: | 0
|
| Processor PLL Lock Resolution: | 1 ms
|
| Fast Burst Timer Count: | 0
|
| |
|
[General-Purpose Input Control]
|
| GPI Select (DEV13): | Level
|
| GPI Select (DEV12): | Level
|
| GPI Polarity (DEV13): | Assert High
|
| GPI Polarity (DEV12): | Assert High
|
| GPI Polarity (DEV11): | Assert High
|
| GPI Polarity (DEV10): | Assert High
|
| GPI Polarity (DEV9): | Assert High
|
| GPI Polarity (DEV8): | Assert High
|
| GPI Polarity (DEV7): | Assert High
|
| GPI Polarity (DEV6): | Assert High
|
| GPI Polarity (DEV5): | Assert High
|
| GPI Polarity (DEV4): | Assert High
|
| GPI Polarity (DEV3): | Assert High
|
| GPI Polarity (DEV2): | Assert High
|
| GPI Polarity (DEV1): | Assert High
|
| GPI Enable (DEV13): | Disabled
|
| GPI Enable (DEV12): | Disabled
|
| GPI Enable (DEV11): | Disabled
|
| GPI Enable (DEV10): | Disabled
|
| GPI Enable (DEV9): | Disabled
|
| GPI Enable (DEV8): | Disabled
|
| GPI Enable (DEV7): | Disabled
|
| GPI Enable (DEV6): | Disabled
|
| GPI Enable (DEV5): | Disabled
|
| GPI Enable (DEV4): | Disabled
|
| GPI Enable (DEV3): | Disabled
|
| GPI Enable (DEV2): | Disabled
|
| GPI Enable (DEV1): | Disabled
|
| |
|
[Device Resource D]
|
| LPT DMA Select: | DACK0
|
| Device 11 IRQ12: | Disabled
|
| Device 11 IRQ1: | Disabled
|
| LPT Port: | Enabled
|
| LPT DMA Monitor: | Disabled
|
| Serial Port B Monitor: | Disabled
|
| Serial Port A Monitor: | Enabled
|
| FDC Monitor: | Disabled
|
| FDC DMA Monitor: | Disabled
|
| DACK7: | Disabled
|
| DACK6: | Disabled
|
| DACK5: | Disabled
|
| DACK3: | Disabled
|
| DACK1: | Disabled
|
| DACK0: | Disabled
|
| |
|
[Device Activity Event Selection A]
|
| Device 5 Reload Select: | Slow Burst Timer
|
| Device 3 Reload Select: | Slow Burst Timer
|
| Device 2 Reload Select: | Slow Burst Timer
|
| Device 1 Reload Select: | Slow Burst Timer
|
| Burst Timer Reload (DEV13): | Disabled
|
| Burst Timer Reload (DEV12): | Disabled
|
| Burst Timer Reload (DEV11): | Disabled
|
| Burst Timer Reload (DEV10): | Disabled
|
| Burst Timer Reload (DEV9): | Disabled
|
| Burst Timer Reload (DEV8): | Disabled
|
| Burst Timer Reload (DEV7): | Disabled
|
| Burst Timer Reload (DEV6): | Disabled
|
| Burst Timer Reload (DEV5): | Disabled
|
| Burst Timer Reload (DEV4): | Disabled
|
| Burst Timer Reload (DEV3): | Disabled
|
| Burst Timer Reload (DEV2): | Disabled
|
| Burst Timer Reload (DEV1): | Disabled
|
| Burst Timer Reload (DEV0): | Disabled
|
| Global Timer Reload (DEV13): | Disabled
|
| Global Timer Reload (DEV12): | Disabled
|
| Global Timer Reload (DEV11): | Enabled
|
| Global Timer Reload (DEV10): | Disabled
|
| Global Timer Reload (DEV9): | Disabled
|
| Global Timer Reload (DEV8): | Enabled
|
| Global Timer Reload (DEV7): | Enabled
|
| Global Timer Reload (DEV6): | Enabled
|
| Global Timer Reload (DEV5): | Disabled
|
| Global Timer Reload (DEV4): | Disabled
|
| Global Timer Reload (DEV3): | Disabled
|
| Global Timer Reload (DEV2): | Disabled
|
| Global Timer Reload (DEV1): | Enabled
|
| Global Timer Reload (DEV0): | Enabled
|
| |
|
[Device Activity Event Selection B]
|
| APMC: | Enabled
|
| Video: | Disabled
|
| Bus Utilization Threshold: | 0%
|
| Bus Utilization Threshold: | 0
|
| IRQ Global Reload: | Disabled
|
| IRQ8# Clock Event: | Disabled
|
| PME Clock Event: | Disabled
|
| KBD/Mouse Global Reload: | Disabled
|
| IRQ Clock Event: | Disabled
|
| IRQ0 Clock Event: | Disabled
|
| |
|
[Device Resource A]
|
| Device 8 EIO: | Disabled
|
| Device 13 EIO: | Disabled
|
| Device 12 EIO: | Disabled
|
| Device 11 KBD: | Enabled
|
| Graphics A/B Seg. Memory: | Disabled
|
| Graphics I/O: | Disabled
|
| Sound Blaster EIO: | Disabled
|
| Linear Frame Buffer Decode: | Disabled
|
| Linear Frame Buffer Mask: | 00000000
|
| Linear Frame Buffer Address: | 0
|
| MS Sound System Decode: | 530h-537h
|
| MS Sound System: | Disabled
|
| Sound Blaster Decode: | 220h-233h
|
| Game Port: | Disabled
|
| Sound Blaster 8/16-bit Decode: | Disabled
|
| MIDI Decode: | 300h-303h
|
| MIDI: | Disabled
|
| |
|
[Device Resource B]
|
| Game Port EIO: | Disabled
|
| KBD EIO: | Disabled
|
| Device 5 EIO: | Disabled
|
| FDC Decode: | Primary (3Fxh)
|
| LPT Controller Decode: | 378h-37Fh, 778h-77Ah
|
| MS Sound System EIO: | Disabled
|
| Device 9 Generic Decode Chip-select: | Disabled
|
| Device 9 EIO: | Disabled
|
| Device 9 Generic Decode Monitor: | Disabled
|
| MIDI EIO: | Disabled
|
| Device 9 Generic Decode Mask: | 0
|
| Device 9 Generic Decode Base: | 0
|
| |
|
[Device Resource C]
|
| Device 7 EIO: | Disabled
|
| Serial Port B Decode: | 2F8h-2FFh (COM2)
|
| Device 6 EIO: | Disabled
|
| Serial Port A Decode: | 3F8h-3FFh (COM1)
|
| Device 10 Generic Decode Chip-select: | Disabled
|
| Device 10 EIO: | Disabled
|
| Device 10 Generic Decode Monitor: | Disabled
|
| Device 10 Generic Decode Mask: | 0
|
| Device 10 Generic Decode Base: | 0
|
| |
|
[Device Resource E]
|
| Device 12 I/O Monitor: | Disabled
|
| Device 12 I/O Decode Mask: | 0
|
| Device 12 I/O Decode Base: | 0
|
| |
|
[Device Resource F]
|
| Device 12 Memory Decode Base: | 0
|
| Device 12 Memory Monitor: | Disabled
|
| Device 12 Memory Decode Mask: | 0
|
| |
|
[Device Resource G]
|
| Device 13 I/O Monitor: | Disabled
|
| Device 13 I/O Decode Mask: | 0
|
| Device 13 I/O Decode Base: | 0
|
| |
|
[Device Resource H]
|
| Device 13 Memory Decode Base: | 0
|
| Device 13 Memory Monitor: | Disabled
|
| Device 13 Memory Decode Mask: | 0
|
| |
|
[Device Resource I]
|
| Generic I/O Decode 0: | Disabled
|
| Generic Decode 0 I/O Mask: | 0
|
| Generic Decode 0 I/O Base: | 0
|
| |
|
[Device Resource J]
|
| Generic I/O Decode 1: | Disabled
|
| Generic Decode 1 I/O Mask: | 0
|
| Generic Decode 1 I/O Base: | 0
|
| |
|
[Miscellaneous Power Management]
|
| PM I/O Space: | Enabled
|
| |
|
[SMBase I/O Ports]
|
| SMBus I/O Base Address: | FC00
|
| |
|
[SMBus Host Configuration]
|
| SMBus Interrupt Select: | SMI#
|
| SMBus Controller Host: | Enabled
|
| |
|
[SMBus Slave Command]
|
| SMBus Host Slave Command: | 0
|
| |
|
[SMBus Slave Shadow Port 1 Address]
|
| SMBus Shadow 1 Slave Address: | 0
|
| Shadow Port 1 R/W: | Disabled
|
| |
|
[SMBus Slave Shadow Port 2 Address]
|
| SMBus Shadow 2 Slave Address: | 0
|
| Shadow Port 2 R/W: | Disabled
|
| |
|
[SMBus Revision]
|
| SMBus Revision: | 0
|