Error-Correction-Chip.jpg (attached)
The rectangular circuit in the center of the uses error-correction techniques that could allow future microprocessors to achieve 30% higher performance/watt. This circuit is one of many research experiments built into this silicon wafer.

DRAM-Setup.jpg (attached)
The research chip under test here experiments with a new type of integrated DRAM, twice as dense as traditional on-chip memories.

FastRx-Chip.jpg
At the center of this silicon chip is an experimental I/O receiver, the most energy efficient to date over 20Gbps.

PowerAmp.jpg
65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation

Transceiver_Full.jpg
90nm CMOS transceiver with an integrated Front End for 802.11agn WLAN applications

Frac-n_Synth_Blue.jpg
S-D Fractional-N frequency synthesizer implemented in 90nm CMOS
