
/*M*                     
//                    INTEL CORPORATION PROPRIETARY INFORMATION
//      This software is supplied under the terms of a license agreement or
//      nondisclosure agreement with Intel Corporation and may not be copied
//      or disclosed except in accordance with the terms of that agreement.
//            Copyright (c) 1995-2000 Intel Corporation.  All Rights Reserved.
//
//
*M*/
/*
 * $Log:   //cospublic004/shareddata/isc/ISC2x/common/src/imb/smic.h.v  $
 * 
 *    Rev 1.2   07 Oct 1999 15:28:18   jpaiasno
 * Added  new BMC transfer state machine code
 *  to KCS interface for IPMI 1.0 conformance
 * 
 *    Rev 1.1   08 Dec 1998 10:55:46   jpaiasno
 * Added code to support async.
 * DPC events from the EMP console.
 * 
 *    Rev 1.4   24 Mar 1998 14:29:36   fkhanx
 * Added Copyright Header
*/
// SMIC hardware register addresses
//
#define SMIC_DATA_REGISTER 0x0CA9       /* SMIC Data Reg. address */
#define SMIC_CNTL_REGISTER 0x0CAA       /* SMIC Control Reg. address */
#define SMIC_FLAG_REGISTER 0x0CAB       /* SMIC Flags Reg. address */

//
// flag register defines
//
#define SMIC_BUSY		0x01
#define SMS_AVAIL		0x04
#define SMM_AVAIL		0x08
#define SMI_AVAIL		0x10
#define TX_DATA_RDY		0x40
#define RX_DATA_RDY		0x80

//
// Defines for delay and timeout values
//
#define SMIC_READY_DELAY	WAIT_5_MS	// how long to wait for SMIC if to come ready
#define BMC_RESPONSE_DELAY	WAIT_10_MS	// how long to wait for a response after sending req
#define BMC_RETRY_DELAY		(60 * WAIT_1_MS)	// how long to wait after an error before retrying

#define MAX_INVALID_RESPONSE_COUNT	2	// number of BMC request send retries 

//
//	SMIC tranfer/receive operation state machine states
//

#define TRANSFER_INIT   0
#define TRANSFER_START  1
#define TRANSFER_NEXT   2
#define TRANSFER_END    3
#define TRANSFER_ABORT  4
#define RECEIVE_INIT    5
#define RECEIVE_START   6
#define RECEIVE_NEXT    7
#define RECEIVE_END     8
#define RECEIVE_ABORT   9
#define MACHINE_END     128

//
// Server Management Software(SMS) Transfer Stream Control Code definition
//
#define SMS_CC_GET_STATUS				0x40
#define SMS_CC_START_TRANSFER			0x41
#define SMS_CC_NEXT_TRANSFER			0x42
#define SMS_CC_END_TRANSFER				0x43
#define SMS_CC_START_RECEIVE            0x44
#define SMS_CC_NEXT_RECEIVE             0x45
#define SMS_CC_END_RECEIVE				0x46
#define SMS_CC_TRANSFER_ABORT			0x47

//
// Server Management Software(SMS) Transfer Stream Status Code definition
//
#define SMS_SC_READY					0x0c0
#define SMS_SC_WRITE_START				0x0c1
#define SMS_SC_WRITE_NEXT				0x0c2
#define SMS_SC_WRITE_END				0x0c3
#define SMS_SC_READ_START				0x0c4
#define SMS_SC_READ_NEXT				0x0c5
#define SMS_SC_READ_END					0x0c6
