-- ***************************************************************************
-- Intel(R) Xeon(R) Processor 7500 Series 8-Core Boundary Scan Descriptor Language 
-- (BSDL) Model, Version 1.0, March 03, 2010
--
-- ***************************************************************************
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-- intellectual property rights is granted by this document. Except as
-- provided in Intel's Terms and Conditions of Sale for such products,
-- Intel assumes no liability whatsoever, and Intel disclaims any express or
-- implied warranty, relating to sale and/or use of Intel products including
-- liability or warranties relating to fitness for a particular purpose,
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-- intellectual property right. Intel products are not intended for use in
-- medical, life saving, or life sustaining applications.
--
-- Intel may make changes to specifications and product descriptions at any
-- time, without notice.
--
-- The Intel(R) Xeon(R) Processor 7500 Series may contain design defects or errors 
-- known as errata which may cause the product to deviate from published
-- specifications. Current characterized errata are available on request.
--
-- Contact your local Intel sales office or your distributor to obtain the
-- latest specifications and before placing your product order.
--
-- Copyright (c) Intel Corporation 2007, 2008, 2009, 2010. Third-party brands and
-- names are the property of their respective owners.
-- ***************************************************************************
--
-- 1. Normal power up sequence must be completed prior to using Boundary Scan logic. 
--
-- 2. PwrGood should be held stable for 34ms before beginning Boundary Scan operations.
--
-- 3. The serial chain for all 9 Xeon7500 TAP blocks are connected in the following way:
--     TDI -> Xeon7500_chipset -> Xeon7500_core0 -> Xeon7500_core1 ->
--            Xeon7500_core2   -> Xeon7500_core3 -> Xeon7500_core4 ->
--            Xeon7500_core5   -> Xeon7500_core6 -> Xeon7500_core7 -> TDO
--
-- 4. TCLK, TMS, TRST_N are all connected in parallel to each TAP. Each TAP has its own Instruction Register.
--
-- 5. Output and bidirectional pins may experience a 1-Tclk glitch during Sample/Preload.
