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README.TXT


CONTENTS
--------	

Itanium_BSDL_9000_C1.txt: 	Dual-Core Intel Itanium Processor 9000 series C1 BSDL File 

Itanium_BSDL_9000_C2.txt: 	Dual-Core Intel Itanium Processor 9000 series C2 BSDL File 

Itanium2_bc_defs.txt: 		BSDL cell definitions


DESCRIPTION
-----------
The Boundary Scan Description Language is a standard method for describing 
essential features of the  ANSI/IEEE 1149.1-1990 compliant devices. For more 
information, please refer to the IEEE Std 1149.1b-1994 document, the supplement 
to the IEEE 1149.1-1990 document, and the IEEE 1149.1a-1993 document.

The Itanium Processor BSDL provides a description of the Itanium processor 
signal pins to be driven and/or sampled, thereby allowing direct control and 
monitoring of processor pins by the system through the TAP (Test Access Port). 

For more information on Itanium 2 processor pin definitions, see the Itanium(R) 
Based Platform Compatible Processors Electrical, Mechanical and Thermal 
Specifications.


REVISION HISTORY:
-----------------
June 2006 Rev 1.1 production release for C1 and C2 steppings
 
COMMENTS:
---------

1. EMTS naming convention uses # for negative logic signals, but # is not a 
recognized BSDL character and have been replaced with the character B in 
signal names in this file.

2. This file describes the Itanium 2 Processor OLGA BSDL model inside the cartridge. 
Pin locations are therefore different from the pin locations in the Itanium2 
Processor datasheet.

3. Strobe inputs (STBP and STBN) are true differential inputs. They must be in opposite
logic states to obtain valid data.
